Mixed-Signal Logic Design Engineer – High-Speed IP

Intel; Phoenix (AZ); On-site; USD 142,000 - 269,000; Full time

Job summary

Intel is seeking a Mixed Signal Logic Design Engineer to shape high-speed IP designs in a collaborative, cross-functional environment. The role emphasizes architecture definition, RTL implementation, and verification across pre- and post-silicon stages.

Responsibilities include developing architecture specifications, coordinating junior designers, and ensuring timing closure while collaborating with physical design and validation teams in the US.

Qualifications

• BS or MS in Electrical Engineering or Computer Engineering with 3+ years of relevant experience.
• Experience with SystemVerilog and digital design concepts (FSMs, timing, CDC).
• Knowledge of computer architecture, analog design, ADC/DAC concepts is a plus.
• Ability to work independently and across multiple clock domains.

Responsibilities

• Develop architecture and microarchitecture specifications for logic components and system architecture decisions.
• Implement specifications in RTL and coordinate junior designers to deliver complex logic blocks.
• Develop behavioral models for analog/mixed-signal blocks using SystemVerilog.
• Run simulations and debug with AMS/logic verification tools.
• Support physical design with synthesis and timing closure.
• Collaborate with pre- and post-silicon validation teams on test plans and issues.

Skills

SystemVerilog

FSM design

Clock-domain design

Digital design

High-speed I/O

Analog/mixed-signal knowledge

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

EDA tools

Job description

Intel is seeking a Mixed Signal Logic Design Engineer to shape high-speed IP designs in a collaborative, cross-functional environment. The role emphasizes architecture definition, RTL implementation, and verification across pre- and post-silicon stages.

Responsibilities include developing architecture specifications, coordinating junior designers, and ensuring timing closure while collaborating with physical design and validation teams in the US.