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Apple, Inc. is seeking a senior Design Verification Engineer to verify RNM/SystemVerilog models for analog/RF blocks inside a large SoC. You will implement self-checking models, develop assertions, and work with analog designers to enable AMS simulations and robust verification.
The role requires strong RNM/SystemVerilog skills, Cadence experience, and a deep understanding of mixed-signal verification. Relocation assistance and comprehensive benefits are offered.
Apple, Inc. is seeking a senior Design Verification Engineer to verify RNM/SystemVerilog models for analog/RF blocks inside a large SoC. You will implement self-checking models, develop assertions, and work with analog designers to enable AMS simulations and robust verification.
The role requires strong RNM/SystemVerilog skills, Cadence experience, and a deep understanding of mixed-signal verification. Relocation assistance and comprehensive benefits are offered.