RF/Analog Mixed-Signal Verification Engineer

Apple, Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple, Inc. is seeking a Design Verification Engineer to verify functionality and performance of our premier SOCs.

You will own RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks inside a large SoC, including self-checking models and AMS environment setup with analog designers. You will debug complex chip digital-on-top testbenches, develop assertions, and ensure specifications are met.

Qualifications

• Bachelor’s degree required.
• Strong fundamentals in analog/RF circuit theory/topologies.
• Experience with RNM coding in SystemVerilog.

Responsibilities

• Development of RNM RF/Analog models in SystemVerilog.
• Develop models with self-checking techniques.
• Assess required model accuracy level depending on verification goals.
• Develop appropriate assertions to ensure analog/digital specs are respected and provide digital verification passing criteria.
• Work with Analog designers setting up AMS simulation environment.
• Debug complex chip digital-on-top testbenches and seek root causes for failures.

Skills

RNM/SystemVerilog

Analog/RF theory

Digital/AMS verification

Self-checking models

Assertions

Education

Bachelor’s degree

Tools

Cadence mixed signal verification

Job description

Apple, Inc. is seeking a Design Verification Engineer to verify functionality and performance of our premier SOCs.

You will own RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks inside a large SoC, including self-checking models and AMS environment setup with analog designers. You will debug complex chip digital-on-top testbenches, develop assertions, and ensure specifications are met.