Senior Mixed-Signal PHY Validation Engineer (Post-Silicon, Hybrid)

Intel Corporation; Folsom (CA); Híbrido; USD 142.000 - 200.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health benefits

Stock bonuses

Retirement plan

Vacation

Descripción de la vacante

Intel Corporation's Hard IP Development Group seeks an engineer to lead mixed signal high-speed PHY post-silicon validation and debug across PCIe, UCIe, DDR, and Ethernet. You will craft test plans, reproduce issues, and collaborate with SOC teams to resolve complex sightings.

You will provide hands-on IP enabling support for PCIe, UCIe, and USB PHYs, working with cross-functional teams in a hybrid role at US locations including Folsom and Santa Clara.

Formación

• BS in Electrical or Computer Engineering or related field required.
• Experience in electrical or bench post-silicon validation with high-speed PHYs (PCIe, USB, UCIe, DDR, Ethernet).
• Experience with lab hardware and software including oscilloscopes, logic analyzers, protocol analyzers, and BERTs.
• Knowledge of PCIe, USB, or Die-to-Die UCIe IO specifications.

Responsabilidades

• Generate test plans and content for mixed signal high-speed PHY post-silicon validation across Clocking, TX, RX blocks.
• Perform IO protocol debug across PCIe, UCIe, DDR, or Ethernet from PHY and firmware perspectives.
• Conduct SOC board design reviews and support post-silicon debug activities.
• Represent IP team during SOC Power-Ons, providing IP enabling support with recipes and firmware.
• Identify clocking and PHY silicon issues, investigate and disposition customer sightings.
• Reproduce customer issues and drive root cause analysis via failure analysis and structured debug.

Conocimientos

High-speed PHY validation

Post-silicon debug

IO specifications PCIe USB UCIe

Lab hardware software

Educación

BS in Electrical/Computer Engineering

Herramientas

Oscilloscopes

Logic Analyzers

Protocol Analyzers

BERTs

Descripción del empleo

Intel Corporation's Hard IP Development Group seeks an engineer to lead mixed signal high-speed PHY post-silicon validation and debug across PCIe, UCIe, DDR, and Ethernet. You will craft test plans, reproduce issues, and collaborate with SOC teams to resolve complex sightings.

You will provide hands-on IP enabling support for PCIe, UCIe, and USB PHYs, working with cross-functional teams in a hybrid role at US locations including Folsom and Santa Clara.