Senior Microarchitecture & RTL Design Engineer - IP/NoC

International Association of Plumbing and Mechanical Officials (IAPMO); Santa Clara, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

IAPMO in Santa Clara, CA is seeking a seasoned Microarchitect and RTL Design Engineer to shape our IP portfolio, focusing on microarchitecture and RTL coding. You will design configurable IPs and work with hardware, software, and verification teams to deliver high-quality IPs.

Join a team tackling high-speed, pipelined designs with power/area optimization and tight integration with NOc/Caches. Strong RTL capability and collaboration are essential.

Qualifications

• Bachelor's or master's in electrical/computer engineering or computer science.
• 8+ years in microarchitecture and RTL development with hands-on experience.
• Proficiency in Verilog and SystemVerilog with exposure to EDA toolchains.

Responsibilities

• Design and develop microarchitectures for configurable IPs.
• Code RTL with focus on performance, power, and area.
• Collaborate with software for configuration requirements and verifications.
• Work with verification teams on assertions, plans, and coverage.

Skills

Verilog

SystemVerilog

NoCs

Caches & memory subsystems

ARM ACE/CHI coherency

Python

Communication skills

Education

BS or MS in Electrical/Computer Engineering or Computer Science

Tools

EDA tools

Python scripts

Job description

IAPMO in Santa Clara, CA is seeking a seasoned Microarchitect and RTL Design Engineer to shape our IP portfolio, focusing on microarchitecture and RTL coding. You will design configurable IPs and work with hardware, software, and verification teams to deliver high-quality IPs.

Join a team tackling high-speed, pipelined designs with power/area optimization and tight integration with NOc/Caches. Strong RTL capability and collaboration are essential.