Senior Memory Systems Engineer: DDR/LPDDR/HBM Innovator

NVIDIA Gruppe

Santa Clara (CA)

Hybrid

USD 184,000 - 357,000

Full time

4 days ago
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Job summary

NVIDIA is seeking a Senior Memory System Engineer to join the ASIC Memory Subsystem team in Santa Clara, CA. You will work across memory controller, PHY, firmware, and platform architects to design high-performance, low-power memory technology for Tegra SoCs.

You will analyze DDR/LPDDR/HBM tech, validate memory implementations, and collaborate with DRAM suppliers and projects across the stack. The role favors autonomous, innovative engineers.

Qualifications

  • Required: degree in Electrical/Computer Engineering or related field.
  • 10+ years in DRAM/memory subsystem design or similar.
  • Strong memory design fundamentals and related technologies.
  • Deep understanding of memory sub system interactions with cache, controller and PHY.
  • Experience with memory failure analysis and validation.

Responsibilities

  • Analyze future DDR/LPDDR/HBM technologies for performance, power, and reliability.
  • Collaborate with ASIC architects, designers, software and firmware teams.
  • Define memory module, package, and PCB layouts for workloads.
  • Debug and bring up memory evaluation and failure issues.
  • Collaborate with DRAM suppliers and industry partners on technology development.

Skills

Memory design
DDR/LPDDR/HBM
ECC algorithm
SI/PI
Team collaboration
Problem solving

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Python
C/C++

Job description

NVIDIA is seeking a Senior Memory System Engineer to join the ASIC Memory Subsystem team in Santa Clara, CA. You will work across memory controller, PHY, firmware, and platform architects to design high-performance, low-power memory technology for Tegra SoCs.

You will analyze DDR/LPDDR/HBM tech, validate memory implementations, and collaborate with DRAM suppliers and projects across the stack. The role favors autonomous, innovative engineers.

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