Senior Memory Systems Integration Engineer - Hybrid Equity

Nvidia Corporation; Santa Clara (CA); Hybrid; USD 196,000 - 311,000; Full time

Job summary

NVIDIA is seeking a senior Memory Systems Engineer in Santa Clara, CA to lead complex memory subsystem bringup, validation, and characterization across HBM/LPDDR technologies. You will own end-to-end memory closure including performance, power, and reliability, collaborating with design, firmware, and validation teams to ensure robust, scalable products.

The role requires deep expertise in memory training, margining, and cross-domain problem solving, with a system-level instinct to anticipate

Qualifications

• BS or MS in EE/CE or equivalent experience.
• 12+ years in HBM/LPDDR or high-speed memory systems with hands-on silicon bringup, characterization, and debug at scale.
• Deep command of SI/PI, timing, margining, and memory training behavior.
• System-level instinct to foresee memory behavior becoming a product problem and resolve it proactively.

Responsibilities

• HBM & LPDDR System Integration and Bringup: drive bringup, characterization, and debug for next-gen SoCs across memory subsystems.
• Full-Stack Memory Closure: own memory performance, power, thermal, and reliability closure across silicon, package, board, and firmware.
• Post-Silicon Margining, VF Shmoo & Correlation: lead margining and correlation work across voltage, temperature, and frequency.
• Memory Debug: training, calibration, SI/PI & stability issues and cross-domain resolution.
• Validation & Characterization Planning: define validation and issue-tracking plans across chip programs.

Skills

Memory systems engineering

SI/PI & timing

Memory training behavior

Education

BS/MS in EE/CE

Job description

NVIDIA is seeking a senior Memory Systems Engineer in Santa Clara, CA to lead complex memory subsystem bringup, validation, and characterization across HBM/LPDDR technologies. You will own end-to-end memory closure including performance, power, and reliability, collaborating with design, firmware, and validation teams to ensure robust, scalable products.

The role requires deep expertise in memory training, margining, and cross-domain problem solving, with a system-level instinct to anticipate