Senior Memory Systems Engineer - DDR/LPDDR/HBM Architect

NVIDIA; United States; On-site; USD 224,000 - 357,000; Full time

Job summary

NVIDIA is seeking a Senior Memory System Engineer to join the ASIC Memory Subsystem team in the United States. You will work with memory controller/PHY, platform architects, firmware, and DRAM suppliers to design high-performance, low-power memory solutions for Tegra SoCs.

The role involves analyzing DDR/LPDDR/HBM technologies, defining memory layouts, and debugging memory evaluation and failure issues. You will contribute to cutting-edge memory tech across collaboration with cross-functional

Qualifications

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering (CE), or related field (or equivalent experience)
• 10 years of proven track record in DRAM design, module design, or memory subsystem design
• Deep understanding of memory design, ECC algorithms, SI and PI in DDR, LPDDR, and HBM
• Strong understanding of memory subsystem interaction with Cache, Memory controller and PHY
• Experience in design, bring-up and validation for memory failure analysis
• Experience with Python, C/C++ for development and memory workload analysis

Responsibilities

• Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for next-gen SOCs
• Collaborate with ASIC Architects, Designers, Software and Firmware teams to drive memory technology requirements for memory controllers
• Define memory module, package, and PCB layouts appropriate to system workloads
• Debug and bring up memory evaluation/validation and failure issues on memory technology
• Collaborate with DRAM suppliers and industry partners to develop memory technologies

Skills

DRAM design

Memory subsystem design

DDR/LPDDR/HBM

Python

C/C++

Memory controller/PHY

ECC algorithm

SI/PI

Education

Electrical Engineering / Computer Engineering degree

Job description

NVIDIA is seeking a Senior Memory System Engineer to join the ASIC Memory Subsystem team in the United States. You will work with memory controller/PHY, platform architects, firmware, and DRAM suppliers to design high-performance, low-power memory solutions for Tegra SoCs.

The role involves analyzing DDR/LPDDR/HBM technologies, defining memory layouts, and debugging memory evaluation and failure issues. You will contribute to cutting-edge memory tech across collaboration with cross-functional