Senior Memory Package Design Engineer — Co-Design Lead

Micron Technology; Boise (ID); On-site; USD 120,000 - 165,000; Full time

Benefits offered by this job

Medical benefits

Paid time off

Paid holidays

Job summary

Micron Technology in Boise, ID seeks a Senior Package Design Engineer to lead co-design activities bridging silicon design, package architecture, and product development for DRAM memory products. You will collaborate with silicon teams, customer-facing units, and OSAT partners to drive new concepts from inception through High Volume Manufacturing.

The role requires 10+ years in memory substrate design or 5+ years with a Master’s degree, with hands-on experience in flip chip, wire bond, BEOL/RDL,

Qualifications

• Master’s degree with 5+ years of industry experience in advanced memory substrate design or Bachelor’s with 10+ years in memory substrate design
• Hands-on proficiency with Cadence Allegro Package Designer+ / Integrity 3D-IC Platform or equivalent tools
• Experience in memory substrate design including flip chip, wire bond, BEOL/RDL flows, substrate stack-up, and routing for high-density packages
• Demonstrated SI/PI collaboration to incorporate simulation feedback into package design
• Experience with OSAT partners, assembly engineering, and cross-functional global teams to deliver designs through HVM

Responsibilities

• Lead co-design activities with silicon design teams, business units, customers, and architecture teams to define product concepts and optimize die floorplans and interconnects
• Define and optimize package architectures for DRAM products, including stack-up, die padlog optimization, wire bond and interconnect schemes, BEOL/RDL flows
• Lead package layout activities and generate design databases, drawings, and manufacturing documentation
• Collaborate with SI/PI teams to interpret parasitic data and drive design optimization and material choices
• Coordinate with OSATs, assembly engineering, and global teams to conduct DFMEA reviews and ensure HVm compliance
• Work with suppliers and architecture teams to advance design rules for next-gen packaging
• Support continuous improvement: design rule systems, competitive analysis, and IP development

Skills

5+ years memory substrate design

EDA tool proficiency

Flip chip & wire bond interconnects

SI/PI collaboration

OSAT/assembly collaboration

Education

Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related interdisciplinary field

Bachelor's degree + 10+ years in memory substrate design

Tools

Cadence Allegro Package Designer+

Integrity 3D-IC Platform

Siemens/MentorXpedition

AutoCAD

Job description

Micron Technology in Boise, ID seeks a Senior Package Design Engineer to lead co-design activities bridging silicon design, package architecture, and product development for DRAM memory products. You will collaborate with silicon teams, customer-facing units, and OSAT partners to drive new concepts from inception through High Volume Manufacturing.

The role requires 10+ years in memory substrate design or 5+ years with a Master’s degree, with hands-on experience in flip chip, wire bond, BEOL/RDL,