Digital Circuit Design Engineer — SRAM & Memory Blocks

Intel Corporation; Folsom (CA); On-site; USD 106,000 - 149,000; Full time

Job summary

Intel in Folsom, CA seeks a Circuit Design Engineer to design and optimize digital circuits for SRAM, register files, memory compilers, and caches. You will perform schematic entry, simulation, and verification to meet power, performance, and area goals.

You will collaborate with architecture and layout teams in the Data Center Group, apply DFT models and memory characterization techniques to drive robust, leakage-aware designs in a fast-paced environment.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field with 1+ year of experience, or a Master’s degree with 3+ months of experience.
• Experience with circuit simulation tools, digital design, schematic entry, and verification.
• Familiarity with power, performance, area optimization and yield.
• Knowledge of memory characterization and DFT models is a plus.

Responsibilities

• Design and optimize digital circuits for SRAM, register files, memory compilers, and caches.
• Perform circuit design, schematic entry, simulation, and verification for major blocks.
• Create block-level DFT models, develop memory test tools, and enhance design flows/methodologies for improved efficiency.
• Collaborate with architecture, layout, and cross-functional teams to ensure optimal circuit performance, power, area, and yield.
• Characterize memory instances and memory compilers to ensure high-quality designs that meet design goals.

Skills

Circuit design

Schematic entry

Simulation

Verification

Power/ performance/ area optimization

Memory characterization

DFT models

Education

Bachelor's degree in Electrical/Computer Engineering

Master’s degree in Electrical/Computer Engineering

Tools

Circuit simulation tools

DFT models

Memory characterization techniques

Job description

Intel in Folsom, CA seeks a Circuit Design Engineer to design and optimize digital circuits for SRAM, register files, memory compilers, and caches. You will perform schematic entry, simulation, and verification to meet power, performance, and area goals.

You will collaborate with architecture and layout teams in the Data Center Group, apply DFT models and memory characterization techniques to drive robust, leakage-aware designs in a fast-paced environment.