Senior Design Engineer - Coherent High-Speed Interconnect

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Job summary

NVIDIA in California seeks a Senior Design Engineer to drive the architecture and implementation of NVLINK-C2C high-speed interconnects for mobile SoCs and GPUs. You will collaborate with architects, external partners, software teams, and circuit designers to deliver a leading interconnect ecosystem.

The role requires 8+ years in design with Verilog/SystemVerilog, RTL, and power optimization, plus strong communication. Hybrid work with competitive pay and benefits is offered.

Qualifications

• BS or equivalent experience in Electrical Engineering or Computer Engineering; advanced degrees (MS, PhD) a plus.
• 8+ years or relevant design experience.
• Knowledge of industry standard interconnect protocols like PCIe, CXL, AXI, CHI.
• Understanding or experience with Link layer stacks including Data link layer and Physical layer.
• Experience with physical layer of interconnects such as Memory (DDR, LPDDR etc...), PCIe, SerDes.
• Experience and knowledge in architecture, RTL design, performance analysis and power optimization.
• Strong working knowledge of Verilog or System Verilog.
• Good communication skills and interpersonal skills; mentoring junior engineers a plus.

Responsibilities

• Work on architecture and design of state-of-the-art high speed coherent interconnects (NVLINK-C2C) for mobile SoCs and GPUs.
• Collaborate with architects, external partners, software engineers, and circuit designers to deliver a class-leading high speed coherent interconnect.
• NVLINK-C2C enables creation of new product classes with NVIDIA partners, built via chiplets, allowing GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon.
• Learn more about NVIDIA’s ultra-fast chip interconnect tech at the NVLINK-C2C page.
• This position offers real impact in a dynamic, technology-focused company affecting product lines from consumer graphics to autonomous vehicles and AI; team spans the globe.

Skills

Verilog/SystemVerilog

RTL design

Communication skills

Mentoring

Power optimization

Education

BS or equivalent in Electrical/Computer Engineering

MS or PhD a plus

Tools

PCIe

CXL

AXI

CHI

DDR/LPDDR memory interface

Job description

NVIDIA in California seeks a Senior Design Engineer to drive the architecture and implementation of NVLINK-C2C high-speed interconnects for mobile SoCs and GPUs. You will collaborate with architects, external partners, software teams, and circuit designers to deliver a leading interconnect ecosystem.

The role requires 8+ years in design with Verilog/SystemVerilog, RTL, and power optimization, plus strong communication. Hybrid work with competitive pay and benefits is offered.