Senior Logic Design Engineer, Cache Coherent Interconnects

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 265,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

NVIDIA Corporation is seeking a Senior Logic Design Engineer to design CPU on-chip/off-chip interconnects, MP coherency, and system caches. You will craft RTL, assist timing closure, and collaborate with verification and implementation teams to meet aggressive performance and power targets.

Requires a Master's degree in a related field and 5+ years in high-performance semiconductor design. Hybrid work arrangement with opportunities across a global team are offered.

Qualifications

• Master's degree is required or equivalent experience.
• 5+ years of experience in processor or related high performance semiconductor designs.
• Verilog expertise and ASIC design flow knowledge (RTL, verification, synthesis, timing).
• Strong communication and interpersonal skills; mentoring junior engineers is a plus.
• Background in computer architecture, cache coherency or high-speed interconnects is helpful.

Responsibilities

• Write readable, high-performance, low-power RTL for a CPU unit.
• Perform synthesis and timing closure; contribute to design documentation.
• Collaborate with verification team to ensure correctness of your unit.
• Work with implementation to meet timing, area, performance and power goals.
• Assist with timing closure of super units.

Skills

Mentoring junior engineers

Strong communication

Collaborative mindset

Timing closure experience

Education

Master's degree in Electrical Engineering, Computer Engineering or Computer Science

Tools

Verilog

DFT

Timing analysis

Job description

We are now looking for a Senior Logic Design Engineer!

As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you'll be doing:

• As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip.
• Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.
• Collaborate with our verification team to verify the correctness of your unit.
• Work with implementation to achieve your timing, area, performance and power goals.
• Assist with timing closure of super units.

What we need to see:

• Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high performance semiconductor designs.
• Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Strong communication and interpersonal skills are required along with the work in a dynamic, global team. Your successful track record of mentoring junior engineers and interns a huge plus.
• A strong background in computer architecture, cache coherency or high speed interconnects is helpful.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

#LI-Hybrid

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.