Senior Silicon Architect: Cache Coherence & 3D Interconnects

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity benefits

Job summary

NVIDIA Corporation in Santa Clara, CA seeks a Senior Logic Design Engineer to drive silicon architecture for next‑gen CPU processors. You will explore dielet partitioning, 2.5D interposers, and die-to-die interfaces, coordinating with architecture, physical design, and packaging teams to meet area, performance, and power goals.

The role requires a Master’s in EE/CE/CS, 8+ years in high‑performance semiconductor design, and deep knowledge of digital design and cache coherency.

Qualifications

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 8+ years of experience in processor or other related high-performance semiconductor designs.
• Deep understanding of digital design, CPU system architecture and ASIC floor-planning.
• Strong background in cache coherency or high-speed interconnects and industry-standard coherency/IO/memory protocols is helpful.
• Knowledge of advanced packaging (TSMC InFO and CoWoS, Intel EMIB), through-silicon via configurations and backside power delivery is preferred, along with Dielet, Interposer, Substrate connectivity.

Responsibilities

• Own the silicon architecture and construction plan for next-generation CPU processors.
• Explore 2D multi-chip module, 2.5D interposer and 3D hybrid-bonded dielet constructions, including IO and compute placement.
• Plan die-to-die and off-chip IO, including UCIe, DRAM and PCIe.
• Work with architecture, logic design, physical design and packaging teams to meet area, performance, power and thermal goals.

Skills

Digital design

CPU architecture

ASIC floor-planning

Cache coherency

Interconnects

Dielet & interposer

Education

Master’s Degree in EE/CE/CS

Job description

NVIDIA Corporation in Santa Clara, CA seeks a Senior Logic Design Engineer to drive silicon architecture for next‑gen CPU processors. You will explore dielet partitioning, 2.5D interposers, and die-to-die interfaces, coordinating with architecture, physical design, and packaging teams to meet area, performance, and power goals.

The role requires a Master’s in EE/CE/CS, 8+ years in high‑performance semiconductor design, and deep knowledge of digital design and cache coherency.