Senior Silicon Architect: 3D Dielet & Interposer

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a Senior Logic Design Engineer to join the CPU Cache Coherent Interconnects Design Team. You will own silicon architecture and construction plans for next-generation CPU processors, including dielet partitioning, floorplanning, and die-to-die interfaces across 2D/2.5D/3D technologies.

You will collaborate with architecture, logic design, physical design and packaging teams to meet area, performance, power and thermal goals, while advancing interconnects and

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 8+ years of experience in processor or other related high-performance semiconductor designs.
• Deep understanding of digital design, CPU system architecture and ASIC floor-planning.
• Strong background in cache coherency or high-speed interconnects and industry-standard coherency/IO/memory protocols is helpful.
• Knowledge of advanced packaging (TSMC InFO and CoWoS, Intel EMIB), through-silicon via configurations and backside power delivery is preferred.

Responsibilities

• Own the silicon architecture and construction plan for next-generation CPU processors.
• Explore 2D multi-chip module, 2.5D interposer and 3D hybrid-bonded dielet constructions, including IO and compute placement across dielets.
• Develop early floorplans and plan die-to-die and off-chip IO (UCIe, DRAM, PCIe).
• Collaborate with architecture, logic design, physical design and packaging teams to meet area, performance, power and thermal goals.

Skills

CPU architecture

ASIC floorplanning

Digital design

Interconnects

Packaging knowledge

Communication skills

Education

Master's degree in Electrical Engineering / Computer Engineering / Computer Science

Job description

NVIDIA Corporation is seeking a Senior Logic Design Engineer to join the CPU Cache Coherent Interconnects Design Team. You will own silicon architecture and construction plans for next-generation CPU processors, including dielet partitioning, floorplanning, and die-to-die interfaces across 2D/2.5D/3D technologies.

You will collaborate with architecture, logic design, physical design and packaging teams to meet area, performance, power and thermal goals, while advancing interconnects and