Director, Circuit Design (Memory)

SBT; San Francisco (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

SBT is confidentially developing advanced compute silicon with a focus on high-performance memory subsystems. The role involves defining architecture, designing memory arrays, and coordinating with CPU, SoC, andFoundry teams to integrate memory IP from early design through production.

Ideal candidates have deep expertise in SRAM, cache memory, register files, timing circuits, and peripheral logic, and can drive multi-silicon programs from concept to tapeout with strong cross-functional

Qualifications

• Extensive expertise in memory circuit design, memory architecture, or custom digital and mixed-signal circuit development.
• Proven ownership of memory IP or memory subsystems across multiple silicon programs, from initial design through tapeout and silicon bring-up.
• Strong 0-to-1 development experience creating new memory architectures, circuits, or reusable IP from a blank-sheet starting point.
• Deep expertise in SRAM, cache memory, register files, memory arrays, sense amplifiers, write drivers, timing circuits, and peripheral logic.
• Strong understanding of transistor-level design, process variation, power reduction, timing closure, signal integrity, and physical implementation.
• Demonstrated ability to work across architecture, RTL, verification, layout, DFT, physical design, foundry, and validation teams to deliver production-ready silicon.

Responsibilities

• Define the architecture and circuit implementation of high-performance memory subsystems for advanced compute silicon.
• Lead the design of memory arrays, peripheral circuits, control logic, and interfaces optimized for power, performance, area, and reliability.
• Drive memory technology decisions across SRAM, cache structures, register files, and other embedded memory applications.
• Partner with CPU, SoC, physical design, verification, and process technology teams to integrate memory IP into complex silicon products.
• Own circuit-level tradeoff analysis, modeling, characterization, and design reviews throughout the development lifecycle.

Skills

Memory circuit design

Memory architecture

Custom digital & mixed-signal

Job description

This confidential startup company is developing advanced compute silicon for artificial intelligence, machine learning, and high-performance computing applications. The company is designing differentiated hardware that relies on high-performance memory technologies to achieve greater bandwidth, efficiency, and scalability. Joining the team offers the opportunity to influence critical circuit architecture, develop foundational silicon IP, and help bring a new generation of compute products from early design through production.

Role

• Define the architecture and circuit implementation of high-performance memory subsystems for advanced compute silicon.
• Lead the design of memory arrays, peripheral circuits, control logic, and interfaces optimized for power, performance, area, and reliability.
• Drive memory technology decisions across SRAM, cache structures, register files, and other embedded memory applications.
• Partner with CPU, SoC, physical design, verification, and process technology teams to integrate memory IP into complex silicon products.
• Own circuit-level tradeoff analysis, modeling, characterization, and design reviews throughout the development lifecycle.

Qualifications

• Extensive expertise in memory circuit design, memory architecture, or custom digital and mixed-signal circuit development.
• Proven ownership of memory IP or memory subsystems across multiple silicon programs, from initial design through tapeout and silicon bring-up.
• Strong 0-to-1 development experience creating new memory architectures, circuits, or reusable IP from a blank-sheet starting point.
• Deep expertise in SRAM, cache memory, register files, memory arrays, sense amplifiers, write drivers, timing circuits, and peripheral logic.
• Strong understanding of transistor-level design, process variation, power reduction, timing closure, signal integrity, and physical implementation.
• Demonstrated ability to work across architecture, RTL, verification, layout, DFT, physical design, foundry, and validation teams to deliver production-ready silicon.