Senior Lead DSP/RTL Design Engineer (FPGA/ASIC)

Infineon Technologies; Irvine (CA); On-site; USD 201,400 - 277,000; Full time

Benefits offered by this job

Incentive plan

Diversity and inclusion initiatives

Job summary

A leading semiconductor firm in Irvine, CA is seeking a Lead Principal Engineer for Digital Design. This role involves implementing DSP algorithms in Verilog/System Verilog and collaborating with teams on hardware architecture. Candidates should have 15+ years of RTL design experience and strong knowledge of fixed-point math and DSP fundamentals. This position offers a competitive salary range between $201,400 and $277,000, plus participation in an incentive plan.

Qualifications

• 15+ years of experience in RTL design.
• Strong knowledge of fixed-point math and digital signal processing fundamentals.
• Proven experience in implementing DSP algorithms on FPGA or ASIC.

Responsibilities

• Implement DSP algorithms in Verilog/System Verilog.
• Collaborate with teams to define hardware architecture.
• Conduct performance analysis optimizing for latency, throughput, power, and area.

Skills

RTL design (Verilog/System Verilog)

Fixed-point math

DSP algorithms

Problem-solving

Teamwork

Education

Bachelor’s or Master’s degree in EE/Computer Engineering

Tools

MATLAB/Simulink/C/C++

EDA tools (e.g., Synopsys Design Compiler)

Job description

A leading semiconductor firm in Irvine, CA is seeking a Lead Principal Engineer for Digital Design. This role involves implementing DSP algorithms in Verilog/System Verilog and collaborating with teams on hardware architecture. Candidates should have 15+ years of RTL design experience and strong knowledge of fixed-point math and DSP fundamentals. This position offers a competitive salary range between $201,400 and $277,000, plus participation in an incentive plan.