Senior FPGA Engineer – DSP/RTL, MIMO Radio Systems

Edison Smart®; Irvine (CA); Presencial; USD 180.000 - 250.000; Jornada completa

Descripción de la vacante

Edison Smart is seeking a Senior/Principal FPGA Engineer for our Irvine, CA office. The role is on-site (5 days a week) with a base salary of 180k–250k plus bonus. You will design and optimize FPGA architectures and implement high‑performance signal processing blocks in RTL, with strong focus on DSP and verification.

Required: proven FPGA design experience, DSP skills, RTL coding and simulation. This position offers a challenging, hands-on environment in a leading wireless communications context.

Formación

• Extensive FPGA design experience required.
• Strong DSP and signal processing background.
• RTL coding and simulation expertise.

Conocimientos

FPGA design

DSP

RTL coding

Descripción del empleo

Edison Smart is seeking a Senior/Principal FPGA Engineer for our Irvine, CA office. The role is on-site (5 days a week) with a base salary of 180k–250k plus bonus. You will design and optimize FPGA architectures and implement high‑performance signal processing blocks in RTL, with strong focus on DSP and verification.

Required: proven FPGA design experience, DSP skills, RTL coding and simulation. This position offers a challenging, hands-on environment in a leading wireless communications context.