Senior FPGA/RTL Design Engineer, Signal Processing

Motorola Solutions; Los Angeles, Northern (CA, KY); Hybrid; USD 195,000 - 235,000; Full time

Benefits offered by this job

Incentive bonus plans

Medical, dental, vision benefits

401K with company match

10 paid holidays

Generous paid time off

Employee stock purchase plan

Parental & family leave

Job summary

Silvus Technologies, a Motorola Solutions subsidiary, seeks a Principal FPGA/RTL Design Engineer – Signal Processing in Los Angeles, CA. The role involves research and development from concept to field deployment on a hybrid schedule with at least three onsite days.

The candidate will lead RTL design, fixed-point DSP, and Xilinx FPGA projects while collaborating with RF and software teams. U.S. person status and background checks are required.

Qualifications

• Bachelor of Science degree in Electrical Engineering, Computer Science, or related field.
• Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; OR 8 years with MS; OR 6 years with PhD.
• Must be a U.S. Person due to U.S. federal contract.
• Experience with fixed-point binary arithmetic and DSP designs.
• Proven experience with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.

Responsibilities

• Digital design architecting for wireless projects.
• Fixed-point DSP design in collaboration with systems engineers.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting; use of logic analyzers.
• Provide support to RF and Software Engineering teams.

Skills

RTL design

FPGA implementation

Xilinx FPGAs

Vivado IDE

Fixed-point DSP

Clock-domain design

Team collaboration

Education

Bachelor of Science in Electrical Engineering

Master of Science in Electrical Engineering

PhD in Electrical Engineering

Tools

Vivado IDE

MATLAB

Job description

Silvus Technologies, a Motorola Solutions subsidiary, seeks a Principal FPGA/RTL Design Engineer – Signal Processing in Los Angeles, CA. The role involves research and development from concept to field deployment on a hybrid schedule with at least three onsite days.

The candidate will lead RTL design, fixed-point DSP, and Xilinx FPGA projects while collaborating with RF and software teams. U.S. person status and background checks are required.