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Microchip Technology Inc. is seeking a Senior Engineer II-Layout to join the Layout Engineering team in San Jose. You will handle highly complex semiconductor layouts, integration, extraction, verification, manufacturability, reliability, and design-closure challenges.
Ideal candidates have 7.5–10 years in custom physical design, analog/digital/mixed-signal, memory, IO, ASIC or SoC layout, and strong problem-solving and cross-functional collaboration skills.
Microchip Technology Inc. is seeking a Senior Engineer II-Layout to join the Layout Engineering team in San Jose. You will handle highly complex semiconductor layouts, integration, extraction, verification, manufacturability, reliability, and design-closure challenges.
Ideal candidates have 7.5–10 years in custom physical design, analog/digital/mixed-signal, memory, IO, ASIC or SoC layout, and strong problem-solving and cross-functional collaboration skills.