Senior IC Layout Engineer – SerDes & Mixed-Signal

Anysilicon; San Jose (CA); Hybrid; USD 130,000 - 190,000; Full time

Job summary

Advanced Micro Devices, Inc. in San Jose, CA is seeking an experienced IC Layout Engineer to help design high-speed SerDes blocks and lead physical design activities across floors, routing, and power.

You will work with remote teams across time zones, contribute to layout methodologies, and push productivity through pcell automation. A strong background in analog/mixed-signal layout and Cadence SKILL is required.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or IC layout training with relevant experience.
• Experience in layout design for 7nm or below.
• Background in analog/mixed-signal layout fundamentals (IR, EM, capacitances).

Responsibilities

• Design high-speed SerDes analog mixed-signal circuits per project specs.
• Implement block-level layouts: floorplanning, power distribution, and signal routing.
• Post-layout performance analysis and integration at block/IP/chip levels.
• Estimate project schedules and report status clearly.
• Contribute to defining layout methodologies and workflows.
• Drive layout productivity improvements including pcell development and automation.
• Supervise layout resources and provide feedback to design teams.

Skills

SerDes design

Analog layout

Floorplanning

Physical design verifications

GDSII flow

Cadence SKILL

Python scripting

Team collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or IC layout training

Tools

Cadence SKILL

Python

Perl

Tcl

Job description

Advanced Micro Devices, Inc. in San Jose, CA is seeking an experienced IC Layout Engineer to help design high-speed SerDes blocks and lead physical design activities across floors, routing, and power.

You will work with remote teams across time zones, contribute to layout methodologies, and push productivity through pcell automation. A strong background in analog/mixed-signal layout and Cadence SKILL is required.