Senior Engineer II - Layout

Microchip Technology; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Microchip Technology Inc. is seeking a Senior Engineer II-Layout to join the Layout Engineering team in San Jose. You will handle highly complex semiconductor layouts, integration, extraction, verification, manufacturability, reliability, and design-closure challenges.

Ideal candidates have 7.5–10 years in custom physical design, analog/digital/mixed-signal, memory, IO, ASIC or SoC layout, and strong problem-solving and cross-functional collaboration skills.

Qualifications

• Bachelor's degree in Electrical, Electronics, Computer Engineering, or Physics.
• 7.5–10 years of semiconductor layout or SoC/ASIC layout experience.
• Experience in floorplanning, device placement, routing, extraction, and physical verification.
• Ability to work with complex design rules and cross-functional teams.

Responsibilities

• Define and execute complex layout architectures, floorplans, and interconnect strategies.
• Coordinate cross-functional technical decisions and ensure layout closure.
• Review floorplans, layouts, and extracted results for release evidence.
• Provide advanced technical guidance while maintaining qualified authority.

Skills

Layout design

Floorplanning

Device placement

Routing

Extraction

Physical verification

DRC/LVS/ERC

Root-cause analysis

Cross-functional collaboration

Signal integrity

Education

Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics

Tools

Cadence

Synopsys

Mentor Graphics

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Join the Layout Engineering team as a Senior Engineer II-Layout supporting highly complex semiconductor physical layout, integration, extraction, verification, manufacturability, reliability, and design-closure challenges. This role is best suited for candidates with 7.5-10 years of relevant experience in semiconductor custom or physical layout, analog, digital, mixed-signal, memory, IO, ASIC, SoC, physical verification, or a closely related area.

Responsibilities:

• Define and execute highly complex layout architectures, floorplans, device structures, interconnect, power distribution, matching, shielding, extraction, and verification strategies within approved scope.
• Integrate circuit, interface, technology, performance, power, area, reliability, manufacturability, design-rule, and schedule requirements.
• Resolve critical layout, connectivity, parasitic, matching, coupling, electromigration, physical-verification, integration, or tapeout-readiness issues through structured root-cause leadership.
• Evaluate evidence quality, uncertainty, risks, dependencies, waivers, and alternative approaches; communicate decision-ready recommendations.
• Coordinate cross-functional technical decisions and layout closure within approved scope.
• Establish reusable layout structures, automation, verification, extraction, design-rule, and release practices.
• Review decision-ready requirements, floorplans, layouts, extracted results, reports, waivers, defects, and release evidence.
• Provide advanced technical guidance while organizational authority remains separately approved.

Requirements/Qualifications:

Minimum qualifications: Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field with 7.5-10 years of relevant experience in semiconductor layout, custom physical design, analog, digital, mixed-signal, memory, IO, ASIC or SoC layout, floorplanning, device placement, routing, extraction, physical verification, or closely related equivalent experience.

Qualified candidates should demonstrate analytical thinking, semiconductor-layout judgment, geometric and spatial reasoning, structured problem solving, verification discipline, root-cause analysis, technical documentation, evidence-based communication, cross-functional collaboration, quality focus, and the ability to work with complex design rules, schematics, devices, interconnect, parasitics, reliability, manufacturing, and signoff information.

Successful candidates are expected to demonstrate:

• Employment stability, reliability, and sustained accountability in prior roles.
• Effective teamwork and cross-functional collaboration.
• Integrity and accuracy in representing qualifications, experience, and credentials.

Preferred Qualifications:

• Experience with semiconductor custom, analog, digital, mixed-signal, memory, IO, pad, RF, ASIC, or SoC layout.
• Experience with floorplanning, device placement, routing, matching, shielding, power distribution, extraction, DRC, LVS, ERC, antenna, density, reliability, or physical-verification closure.

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