Senior IP Design Lead for SoC & Pre-Silicon

Hardware FYI; Boxborough, Northern (MA, KY); Hybrid; USD 140,000 - 230,000; Full time

Job summary

AMD seeks a Senior IP Design lead to drive pre-silicon IP development, guiding a team of engineers across architecture, verification, and SOC integration. You will ensure first-pass silicon success and coordinate with DFT, physical design, and firmware teams to deliver robust IP subsystems with third-party integrations.

The role requires deep experience in RTL design, power-gating techniques, and strong communication skills to lead multi-geography teams and meet program commitments.

Qualifications

• Significant full-time experience in IP hardware design.
• Experience with embedded processors and data fabric architectures.
• Prior technical leadership experience; subject matter expert.

Responsibilities

• Provide guidance on technical issues faced by the design team.
• Plan team deliverables throughout the program.
• Design IP subsystems with integration of AMD and other 3rd party IP (ARM, DSPs, NOCs).
• Contribute to specification and quality checks (lint, CDC, and power rule checks) of power-gated digital designs.
• Work with IP and SOC teams to support verification, implementation (synthesis, constraints, timing analysis), and delivery to SOC.
• Collaborate with SOC teams to support IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up.

Skills

IP hardware design

embedded processors

Verilog

SystemVerilog

RTL design

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

Verilog simulation

lint tools

CDC/RDC tools

Job description

AMD seeks a Senior IP Design lead to drive pre-silicon IP development, guiding a team of engineers across architecture, verification, and SOC integration. You will ensure first-pass silicon success and coordinate with DFT, physical design, and firmware teams to deliver robust IP subsystems with third-party integrations.

The role requires deep experience in RTL design, power-gating techniques, and strong communication skills to lead multi-geography teams and meet program commitments.