Senior IO/PHY Verification Lead (UVM/SystemVerilog)

Infobahn Softworld Inc; Santa Clara (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Infobahn Softworld Inc. is seeking a seasoned verification lead with strong IO/PHY verification focus in California. The role emphasizes IP verification, UVM and SystemVerilog, leading DV teams and driving new directions across world-class DV groups.

The candidate will define verification plans, create UVM-based testbenches, validate interfaces like PCIe, USB and memory protocols, and mentor engineers across geographies to deliver bug-free designs.

Qualifications

• Significant experience leading DV teams in IO/PHY verification.
• Extensive background in IP verification, UVM, and SystemVerilog.
• Proven ability to define DV plans and guide execution.

Responsibilities

• Define verification plan and provide technical direction to execution teams.
• Comprehend AMS, Firmware and design specs; collaborate on a DV plan.
• Create UVM/SystemVerilog based testbenches and tests.
• Ensure the design is bug free.
• Lead Formal verification.
• Understand PCIe, USB, DDR/LPDDR and Ethernet interfaces.
• Support post-silicon teams for product performance, power and debug/resolution.

Skills

IO/PHY knowledge

IP verification

UVM

SystemVerilog

Testbench development

Team leadership

Education

Bachelor's or Master's degree in related discipline

Job description

Infobahn Softworld Inc. is seeking a seasoned verification lead with strong IO/PHY verification focus in California. The role emphasizes IP verification, UVM and SystemVerilog, leading DV teams and driving new directions across world-class DV groups.

The candidate will define verification plans, create UVM-based testbenches, validate interfaces like PCIe, USB and memory protocols, and mentor engineers across geographies to deliver bug-free designs.