Design Verification Engineer

7Rays Semiconductors; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

7Rays Semiconductors is seeking a motivated Design Verification Engineer to join our Interface IP DV team. You will work closely with architects, designers, and vendors to validate functional correctness and performance across the hardware-software stack.

This role requires strong technical expertise and the ability to solve complex verification challenges in a fast-paced semiconductor environment, focusing on end-to-end verification activities for various IP subsystems.

Qualifications

• Strong expertise in SystemVerilog and UVM.
• Experience with IP/Sub-system verification in complex SoC environments.
• Solid understanding of protocols such as PCIe and Ethernet.
• Experience working with ARM/ARC-based CPU subsystems.
• Knowledge of coverage-driven verification methodologies.
• Strong debugging and problem-solving skills.
• Excellent collaboration and communication abilities.

Responsibilities

• Own end-to-end verification activities for IP subsystems.
• Develop and maintain UVM/SystemVerilog-based verification environments.
• Collaborate with Integration and SoC DV teams for seamless interoperability.
• Drive coverage closure and verification sign-off.

Skills

SystemVerilog

UVM

Debugging

Problem-solving

Collaboration

Communication

Job description

Overview

We are seeking a highly motivated Design Verification Engineer to join our Interface IP DV team. In this role, you will collaborate closely with architects, designers, and external vendors to ensure that architecture requirements are fully implemented across IP subsystems and interfaces. You will play a critical role in validating functional correctness and performance across the complete hardware-software stack.

This position requires strong technical expertise, creativity, and the ability to solve complex verification challenges in a fast-paced semiconductor environment.

Responsibilities

• Own end-to-end verification activities for one or more IP subsystems, including:
• Ethernet
• CPU subsystems (ARC/ARM)
• Low-power peripherals
• Sensors
• Understand vendor IP configurations and manage technical handshakes with internal IP teams.
• Develop and maintain robust UVM/SystemVerilog-based verification environments to ensure:
• Functional correctness
• Performance validation
• Compliance with IP specifications
• Collaborate with Integration and SoC DV teams to validate seamless interoperability of external IPs within the broader chip architecture.
• Drive coverage closure and verification sign-off by:
• Analyzing coverage gaps
• Ensuring comprehensive validation across corner cases and stress scenarios

Qualifications

• Strong expertise in SystemVerilog and UVM
• Experience with IP/Sub-system verification in complex SoC environments
• Solid understanding of protocols such as PCIe and Ethernet
• Experience working with ARM/ARC-based CPU subsystems
• Knowledge of coverage-driven verification methodologies
• Strong debugging and problem-solving skills
• Excellent collaboration and communication abilities