Senior Design Verification Engineer

Synstack Technologies; United States; On-site; USD 120,000 - 170,000; Full time

Job summary

Synstack Technologies is seeking DV engineers to verify complex internal IP blocks within SoC environments, including compute engines and accelerators.

You will develop UVM-based verification environments, create test plans and coverage models, perform RTL functional verification, and debug RTL/testbench issues to drive coverage closure.

Strong skills in SystemVerilog/UVM, block-level verification, and experience with Verdi or DVE are required, with exposure to low-power verification a plus.

Qualifications

• Strong hands-on with SystemVerilog and UVM.
• Experience in block-level verification.
• Good understanding of digital design fundamentals.
• Experience with debug tools (Verdi, DVE, etc.)

Responsibilities

• Develop and maintain UVM-based verification environments
• Create test plans, testcases, and coverage models
• Perform functional verification of RTL designs
• Debug RTL and testbench issues
• Drive coverage closure (functional + code)

Skills

SystemVerilog

UVM

Block-level verification

Digital design fundamentals

Debug tools (Verdi, DVE)

Tools

Verdi

DVE

UPF

AXI/AHB/APB

Job description

We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Key Responsibilities:

• Develop and maintain UVM-based verification environments
• Create test plans, testcases, and coverage models
• Perform functional verification of RTL designs
• Debug RTL and testbench issues
• Drive coverage closure (functional + code)

Required Skills:

• Strong hands-on with System Verilog and UVM
• Experience in block-level verification
• Good understanding of digital design fundamentals
• Experience with debug tools (Verdi, DVE, etc.)

Good to Have:

• Exposure to low-power verification (UPF)
• Experience with AMBA protocols (AXI/AHB/APB)