Senior IC Package Mechanical FEA Engineer (MCM/3DIC)

Broadcom; San Jose (CA); On-site; USD 108,000 - 173,000; Full time

Benefits offered by this job

401K with company match

Employee Stock Purchase Program (ESPP)

Paid holidays

Vacation time

Job summary

Broadcom is seeking an experienced package mechanical FEA engineer for very large and complex packages used in AI, HPC, networking, and 5G devices. You will join a worldwide R&D team to design high-performance package designs for ASICs and influence mechanical trade-offs across multiple domains.

You will work on advanced co-packaged technology and multi-chip-module packaging, collaborating with design, reliability, and manufacturing teams to optimize warpage, stress, thermal, and electrical

Qualifications

• Bachelor’s in Mechanical Engineering with 8+ years FEA experience
• Master’s in Mechanical Engineering with 6+ years FEA experience
• PhD in Mechanical Engineering with 3+ years FEA experience
• Ability to evaluate numerical simulation results against first principles
• Ability to calibrate modeling with empirical data
• Experience with Ansys Classic/Mechanical preferred

Responsibilities

• Design responsibility for mechanical design aspects of ASIC packages
• Use advanced FEA to quantify and optimize reliability and manufacturing
• Measure and experiment to validate understanding and improve model accuracy
• Collaborate closely with package designers, reliability and manufacturing partners
• Schedule and track your work across 4+ projects simultaneously
• Create presentations for and present to engineers, managers, senior management, customers, and vendors
• Document design rules and guidelines

Skills

FEA modeling

Mechanical design

Presentation skills

Education

Bachelor's in Mechanical Engineering

Master's in Mechanical Engineering

PhD in Mechanical Engineering

Tools

Ansys Classic/Mechanical

Job description

Broadcom is seeking an experienced package mechanical FEA engineer for very large and complex packages used in AI, HPC, networking, and 5G devices. You will join a worldwide R&D team to design high-performance package designs for ASICs and influence mechanical trade-offs across multiple domains.

You will work on advanced co-packaged technology and multi-chip-module packaging, collaborating with design, reliability, and manufacturing teams to optimize warpage, stress, thermal, and electrical