Lead High-Speed SerDes Layout Engineer

Hardware FYI; San Jose, Northern (CA, KY); Hybrid; USD 140,000 - 210,000; Full time

Job summary

AMD’s SerDes Technology Group seeks an experienced analog/mixed-signal layout design engineer with supervisory responsibilities in San Jose, CA. The role focuses on high-speed layout of SerDes circuits, with block-level implementation, post-layout analysis, and cross-site collaboration to enable future CPU/GPU connectivity.

The ideal candidate has strong layout fundamentals, experience with high-speed routing, LVS/DRC, and familiarity with Cadence SKILL; knowledge of PI/PLL layouts in FInFET

Qualifications

• Bachelor degree in EE/CE or IC layout required.
• Strong fundamentals in analog/mixed-signal layout.
• Experience with high-speed SerDes blocks and PLLs is a plus.

Responsibilities

• Layout design of high-speed SerDes analog/mixed-signal circuits per specs.
• Block-level physical implementation: floor-planning, PDN, routing.
• Participate in post-layout circuit performance analysis.
• Support integration at block/IP/chip levels and schedule tracking.
• Contribute to layout methodology, flow, and productivity improvements.

Skills

High-speed layout

Analog layout

Collaborative team work

Problem solving

Education

Bachelor's degree in EE/CE or IC layout training certificate

Tools

Cadence SKILL

Perl

Python

Tcl

Job description

AMD’s SerDes Technology Group seeks an experienced analog/mixed-signal layout design engineer with supervisory responsibilities in San Jose, CA. The role focuses on high-speed layout of SerDes circuits, with block-level implementation, post-layout analysis, and cross-site collaboration to enable future CPU/GPU connectivity.

The ideal candidate has strong layout fundamentals, experience with high-speed routing, LVS/DRC, and familiarity with Cadence SKILL; knowledge of PI/PLL layouts in FInFET