Senior IC Layout design Engineer

Anysilicon; San Jose (CA); Hybrid; USD 130,000 - 190,000; Full time

Job summary

Advanced Micro Devices, Inc. in San Jose, CA is seeking an experienced IC Layout Engineer to help design high-speed SerDes blocks and lead physical design activities across floors, routing, and power.

You will work with remote teams across time zones, contribute to layout methodologies, and push productivity through pcell automation. A strong background in analog/mixed-signal layout and Cadence SKILL is required.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or IC layout training with relevant experience.
• Experience in layout design for 7nm or below.
• Background in analog/mixed-signal layout fundamentals (IR, EM, capacitances).

Responsibilities

• Design high-speed SerDes analog mixed-signal circuits per project specs.
• Implement block-level layouts: floorplanning, power distribution, and signal routing.
• Post-layout performance analysis and integration at block/IP/chip levels.
• Estimate project schedules and report status clearly.
• Contribute to defining layout methodologies and workflows.
• Drive layout productivity improvements including pcell development and automation.
• Supervise layout resources and provide feedback to design teams.

Skills

SerDes design

Analog layout

Floorplanning

Physical design verifications

GDSII flow

Cadence SKILL

Python scripting

Team collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or IC layout training

Tools

Cadence SKILL

Python

Perl

Tcl

Job description

Advanced Micro Devices, Inc, 2100 Logic Drive, San Jose, CA 95124

Job Description:

At AMD, we harness technology to tackle the world's most pressing challenges, from healthcare advancements to AI innovations. Join us in shaping the future through cutting-edge processor design and product development, and advance your career while contributing to technology that propels the world forward.

Responsibilities:

• Design high-speed, high-performance SerDes analog mixed‑signal circuits according to project specifications.
• Implement block‑level physical designs, including floor‑planning, power distribution, and signal routing.
• Engage in post‑layout circuit performance analysis and integration activities at block/IP/chip levels.
• Estimate project schedules, track progress, and report status clearly.
• Contribute to defining layout methodologies and workflows.
• Drive initiatives for layout productivity improvements, including pcell development and automation.
• Supervise layout resources, assess layout quality, and provide feedback to design teams.

Qualifications:

• Bachelor's degree in Electrical Engineering/Computer Engineering or equivalent IC layout training with relevant experience.

Skills:

• Experience in layout design for lower process nodes (7nm or below).
• Strong understanding of analog and mixed‑signal layout fundamentals, including IR, EM, capacitances, and RC delay.
• Proficient in high-speed signal routing and shielding techniques.
• Skilled in physical design verifications (LVS/DRC/ERC/ANT/ESD).
• Familiarity with circuit design concepts and IC manufacturing processes.
• Experience with high-speed SerDes blocks and PLLs in advanced Fin‑FET processes is advantageous.
• Knowledge of digital integration flows and Cadence SKILL programming, as well as other languages like Perl, Python, or Tcl.
• Excellent communication skills and ability to collaborate with remote teams across different time zones.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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