Senior HSIO Verification Engineer – Equity Eligible

NVIDIA AI; Westford (MA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Design Verification Engineer in Westford, MA to verify HSIO controllers and interconnect IP across IP/sub-system levels using advanced DV methodologies (UVM). You will craft test plans, build verification environments, and collaborate with architects and design teams to ensure robust silicon delivery.

The role emphasizes strong SystemVerilog/UVM expertise, debugging skills, and excellent communication.

Qualifications

• 5+ years of relevant experience in ASIC/SoC verification.
• Experience at Unit/Sub-system/SOC level with SystemVerilog and UVM.
• Expertise in verification of IP or interconnect protocols (Ethernet, USB, SATA).
• Experience with random stimulus, functional coverage, and assertion-based verification (UVM).
• Excellent debugging, analytical, and problem solving skills.
• Strong communication and collaboration skills.

Responsibilities

• Verify ASIC design, architecture, golden models and micro-architecture of High Speed I/O controllers (Ethernet, NVLink) at IP/sub-system levels using UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage-driven verification.
• Define verification scope, develop test plans and infrastructure to verify design correctness.
• Collaborate with architects, designers, and verification teams across silos to accomplish tasks.

Skills

SystemVerilog

UVM

Test planning

Debugging

Communication

Education

Bachelor’s or Master’s Degree

Tools

Verification tools

Job description

NVIDIA is seeking a Senior Design Verification Engineer in Westford, MA to verify HSIO controllers and interconnect IP across IP/sub-system levels using advanced DV methodologies (UVM). You will craft test plans, build verification environments, and collaborate with architects and design teams to ensure robust silicon delivery.

The role emphasizes strong SystemVerilog/UVM expertise, debugging skills, and excellent communication.