Senior ASIC Verification Engineer — HSIO & IP (Equity)

NVIDIA; Town of Westford (WI); On-site; USD 150,000 - 260,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA in Wisconsin is seeking a Senior Design Verification Engineer to verify the design and implementation of High Speed I/O controllers for SOCs and GPUs. You will work on architecture verification across IP/sub-systems with advanced DV methodologies.

Base salary depends on location and level; equity and benefits are offered. The role emphasizes SystemVerilog, UVM, and cross-functional collaboration with architects and silicon teams to ensure correct verification of complex interconnects like

Qualifications

• Bachelor's or Master's Degree with 5+ years of relevant experience.
• Experience at Unit/Sub-system/SOC level and expertise in SystemVerilog, UVM.
• Expertise in verification of IP or interconnect protocols (Ethernet, USB, SATA).
• Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies (UVM) and exposure to industry standard verification tools for simulation
• Excellent debugging, analytical, and problem solving skills
• Great communication and collaboration skills to interact within the team and across functional teams

Responsibilities

• Be responsible for the verification of ASIC design, architecture, golden models and micro-architecture of High Speed I/O controllers, like Ethernet and NVLink, at IP/sub-system levels using advanced DV methodologies such as UVM.
• Building reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Understanding the design specification and implementation, defining the verification scope, developing test plans, tests, and the verification infrastructure used to verify the correctness of the design.
• Collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Skills

SystemVerilog

UVM

IP verification

Interconnect protocols

Debugging

Communication

Perl

Python

Education

Bachelor's or Master's degree

Job description

NVIDIA in Wisconsin is seeking a Senior Design Verification Engineer to verify the design and implementation of High Speed I/O controllers for SOCs and GPUs. You will work on architecture verification across IP/sub-systems with advanced DV methodologies.

Base salary depends on location and level; equity and benefits are offered. The role emphasizes SystemVerilog, UVM, and cross-functional collaboration with architects and silicon teams to ensure correct verification of complex interconnects like