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AMD in Santa Clara, CA is seeking an HSIO Validation Engineer to validate high-speed interfaces across CPU and GPU platforms, collaborating with PHY design, firmware, and platform teams to ensure quality and readiness for next-gen technologies.
You will execute validation plans for PCIe Gen5/Gen6/Gen7, UALink, Ethernet, and other interfaces, develop automation, analyze signal integrity, and document findings for stakeholders.
AMD in Santa Clara, CA is seeking an HSIO Validation Engineer to validate high-speed interfaces across CPU and GPU platforms, collaborating with PHY design, firmware, and platform teams to ensure quality and readiness for next-gen technologies.
You will execute validation plans for PCIe Gen5/Gen6/Gen7, UALink, Ethernet, and other interfaces, develop automation, analyze signal integrity, and document findings for stakeholders.