Senior High-Speed IO Validation Engineer (PCIe/CXL)

AMD; Santa Clara (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

AMD is seeking a principal validation engineer to join our datacenter CPU post-silicon validation team, focusing on high-speed IO, PCIe and CXL, and multi-socket inter-die interfaces. You will drive feature enablement, validation plans, and post-silicon infrastructure across server products.

You will collaborate with cross-functional teams, develop test content, and debug complex SoC and system-level issues, while mentoring others and advancing validation methodologies in a fast-paced,

Qualifications

• BSEE/CSE/CS required with 7+ years of experience or
• MSEE/CSE/CS with 5+ years of experience.
• Experience in validation methodologies and infrastructure.

Responsibilities

• Develop and execute feature enablement and validation plans for SoC and system-level high-speed IO in AMD Server products.
• Create test content for focus and system-level stress testing of IO domains and cross-product validation.
• Develop post-silicon validation infrastructure (software, hardware, automation, and lab setup).
• Debug and drive root-cause analysis for SoC related issues.
• Collaborate with cross-functional teams to improve validation tools and processes.

Skills

C/C++ programming

Python scripting

SoC validation

Lab equipment

Oscilloscopes

Education

BSEE/CSE/CS: 7+ yrs

MSEE/CSE/CS: 5+ yrs

Tools

PCIe/Gen5/6+

CXL/UCIe

Server OS (Linux, Windows)

Job description

AMD is seeking a principal validation engineer to join our datacenter CPU post-silicon validation team, focusing on high-speed IO, PCIe and CXL, and multi-socket inter-die interfaces. You will drive feature enablement, validation plans, and post-silicon infrastructure across server products.

You will collaborate with cross-functional teams, develop test content, and debug complex SoC and system-level issues, while mentoring others and advancing validation methodologies in a fast-paced,