HSIO Validation Lead — Silicon Co-Design (Equity Options)

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Job summary

NVIDIA is seeking an experienced silicon validation engineer to own post-silicon bring-up, characterization, and debugging of high-speed interfaces across GPUs, CPUs, and SoCs. You will define validation strategies, set coverage and margining criteria, and drive root-cause analysis across protocol, firmware, and driver interactions.

Your work will ensure robust platform interoperability and reduce risk to production. You will build AI-enabled debug flows and contribute to future silicon success.

Qualifications

• 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.
• Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar HSIO technologies.
• Strong signal integrity fundamentals including SERDES, link training, and timing.
• Hands-on lab depth with oscilloscopes, protocol analyzers, and silicon debug tools.

Responsibilities

• Own post-silicon bring-up, characterization, validation, and debug of HSIO interfaces across NVIDIA GPUs/CPUs/SoCs.
• Define validation strategy and set test coverage, margining methodology, and stress criteria.
• Drive root cause analysis across protocol behavior, firmware, and driver interactions; own fixes through to confirmation.
• Translate silicon learnings into methodology and coverage improvements for future products.

Skills

Silicon validation

High-speed interface debugging

Troubleshooting

Stack debugging

Statistical proficiency

Education

BS/MS in Electrical/Computer/Systems Engineering

Tools

Oscilloscopes

Protocol analyzers

Logic analyzers

BERTs

Exercisers

Job description

NVIDIA is seeking an experienced silicon validation engineer to own post-silicon bring-up, characterization, and debugging of high-speed interfaces across GPUs, CPUs, and SoCs. You will define validation strategies, set coverage and margining criteria, and drive root-cause analysis across protocol, firmware, and driver interactions.

Your work will ensure robust platform interoperability and reduce risk to production. You will build AI-enabled debug flows and contribute to future silicon success.