Senior High-Speed Interface Engineer – Tech Lead

Analog Devices; Wilmington (MA); On-site; USD 110,385 - 151,808; Full time

Benefits offered by this job

Medical insurance

Vision insurance

Dental insurance

401k

Paid time off

Job summary

Analog Devices, Inc. in United States is seeking a Senior Product Development Engineer to own high-speed interface validation from bring-up through release across complex mixed-signal ICs.

The role requires collaboration with design, test, and applications teams to ensure robust performance from first silicon through release, while mentoring junior engineers and improving lab automation to increase throughput.

Qualifications

• 5+ years of experience in high-speed interface validation and mixed-signal development.
• Strong lab skills in eye diagrams, jitter, BER, and high-speed probing.
• Experience with FPGA-based validation platforms and embedded software/firmware workflows.

Responsibilities

• Interface bring-up, validation, and readiness across mixed-signal ICs.
• Lead qualification planning and test condition definitions.
• Characterize interfaces across PVT and configuration space.
• Perform signal integrity and protocol-level debugging.
• Correlate bench data to simulation and support ATE yield and test content.
• Develop validation frameworks using Python or MATLAB to improve throughput.
• Mentor junior engineers and guide cross-functional teams.
• Communicate risks and status to design, test, and program stakeholders.

Skills

High-Speed Interface Validation

Signal Integrity Measurements

Lab Automation & Data Analysis

Mixed-Signal Product Development

Qualification & Test Leadership

Production Validation & Throughput

Cross-Functional Collaboration

Education

Master’s degree in Electrical Engineering

Job description

Analog Devices, Inc. in United States is seeking a Senior Product Development Engineer to own high-speed interface validation from bring-up through release across complex mixed-signal ICs.

The role requires collaboration with design, test, and applications teams to ensure robust performance from first silicon through release, while mentoring junior engineers and improving lab automation to increase throughput.