Senior High-Speed Analog/Mixed-Signal Architect

Monolithic Power Systems, Inc.; San Jose (CA); On-site; USD 170,000 - 250,000; Full time

Job summary

Monolithic Power Systems, Inc. in San Jose, CA is seeking a Principal High Speed Analog/Mixed Signal Designer to own and advance high-speed block and chip-level circuits.

You will drive design, modeling, and verification for critical data-path blocks and collaborate with digital teams to meet performance, power, and timing targets. The role emphasizes leadership in pre-silicon verification, model creation, and close interaction with layout and test teams for silicon bring-up.

Qualifications

• MS EE and 7+ years or PhD EE and 5+ years experience in analog/mixed-signal design
• Experience in high-speed analog circuits like Transmitter, Receiver, PLL, DLL, PI or clock distribution
• Experience with DDR4/5 or PCIe memory interfaces and Verilog-A/Verilog modeling

Responsibilities

• Own high speed analog/mixed-signal designs at chip and block level
• Design, simulate and characterize high-performance circuits
• Create models for design tradeoffs and verification simulations
• Collaborate with digital teams to define architecture and plans
• Assist layout team to demonstrate post-extraction performance
• Document analyses and test plans for silicon bring-up and verification
• Mentor junior designers and contribute to process improvements

Skills

High-speed analog/mixed-signal design

Transmitter/Receiver/PLL/DLL/clocking

Memory interfaces (DDR4/5, PCIe)

Circuit modeling and tradeoffs

Mentoring junior designers

Education

MS EE

PhD EE

Tools

Verilog-A

Verilog

MATLAB

Job description

Monolithic Power Systems, Inc. in San Jose, CA is seeking a Principal High Speed Analog/Mixed Signal Designer to own and advance high-speed block and chip-level circuits.

You will drive design, modeling, and verification for critical data-path blocks and collaborate with digital teams to meet performance, power, and timing targets. The role emphasizes leadership in pre-silicon verification, model creation, and close interaction with layout and test teams for silicon bring-up.