Senior High-Speed Analog Layout Engineer

Emploive; San Jose (CA); Hybrid; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, a fast-growing semiconductor startup, is seeking a High-Speed Analog Layout Design Engineer to drive the layout of analog/mixed-signal IP blocks such as ADCs, DACs, and PLLs for high-performance optical communication systems.

As a key member of the AMS design team, you will mentor junior layout engineers, collaborate with circuit designers and CAD/PDK teams, and ensure first-pass silicon success through rigorous LVS/DRC checks and optimized floor planning.

Qualifications

• 10+ years analog/mixed-signal layout in CMOS/FinFET.
• Led IP layout macros or full-chip layouts at FinFET nodes.
• Experience with TSMC N3/N5/N7/N16 processes.
• Strong knowledge of LOD, WPE, OSE, LDE effects.

Responsibilities

• Lead physical layout of ADCs, DACs, PLLs from floorplanning to verification.
• Collaborate with schematic designers for optimal layouts.
• Mentor junior layout engineers across time zones.
• Perform LVS, DRC, PERC, ERC checks and signoff.
• Contribute to top-level floor planning and power distribution.
• Assist in layout reviews and drive quality and schedules.
• Support automation via SKILL, TCL, Python.

Skills

Analog layout

Mentoring

Collaboration

Schematic integration

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Celero Communications, a fast-growing semiconductor startup, is seeking a High-Speed Analog Layout Design Engineer to drive the layout of analog/mixed-signal IP blocks such as ADCs, DACs, and PLLs for high-performance optical communication systems.

As a key member of the AMS design team, you will mentor junior layout engineers, collaborate with circuit designers and CAD/PDK teams, and ensure first-pass silicon success through rigorous LVS/DRC checks and optimized floor planning.