Lead High-Speed Analog Layout Architect for IP Macros

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Foundational startup role

International team culture

Growth opportunities

Job summary

Celero Communications, Inc. in San Jose, CA, seeks a Principal High-Speed Analog Layout Design Engineer to drive the layout of complex analog/mixed-signal IP blocks for advanced optical communication systems.

This hands-on role leads floor planning, LVS/DRC, and top-level integration, while mentoring junior engineers across time zones. You will collaborate with circuit designers and CAD/PDK teams to ensure first-pass silicon success, tackle layout verification, and push performance, matching,

Qualifications

• 10+ years of hands-on analog/mixed-signal layout in advanced CMOS/FinFET technologies.
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred).
• Experience with 1+ year at TSMC FinFET nodes (N3/N5/N7/N16).
• Familiarity with LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules.

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through final verification.
• Collaborate with schematic designers to optimize performance, matching, symmetry, and reliability.
• Mentor junior layout engineers across multiple time zones and enforce best practices.
• Perform LVS, DRC, PERC, ERC checks and signoffs using industry tools.
• Contribute to chip-level planning, top-level floor planning, power grid, and signal routing.
• Participate in layout design reviews and provide technical leadership on quality and schedules.
• Assist automation initiatives through scripting (SKILL, TCL, Python).

Skills

Analog Layout

Mixed-Signal

CMOS FinFET

Floor Planning

LVS/DRC

Cadence Virtuoso

Calibre

Scripting (TCL/Python)

Leadership

International Collaboration

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Celero Communications, Inc. in San Jose, CA, seeks a Principal High-Speed Analog Layout Design Engineer to drive the layout of complex analog/mixed-signal IP blocks for advanced optical communication systems.

This hands-on role leads floor planning, LVS/DRC, and top-level integration, while mentoring junior engineers across time zones. You will collaborate with circuit designers and CAD/PDK teams to ensure first-pass silicon success, tackle layout verification, and push performance, matching,