Senior High-Speed Analog Layout Architect

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. in Irvine, CA is seeking a Principal High-Speed Analog Layout Design Engineer to lead the layout of complex analog/mixed-signal IP blocks integral to advanced optical communications systems.

You will mentor junior engineers, drive floor planning and power grid implementation, and coordinate with circuit designers, CAD/PDK teams, and international teams to ensure first-pass silicon success.

Qualifications

• 10+ years of hands-on analog/mixed-signal layout in CMOS/FinFET.
• Leadership in owning IP layout macros or full-chip layouts.
• Experience with TSMC FinFET process nodes (N3/N5/N7/N16).
• Strong knowledge of LVS/DRC and parasitic minimization.
• Excellent communication and cross-team collaboration.

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through final verification.
• Collaborate with schematic designers to optimize layout performance and reliability.
• Mentor junior layout engineers across multiple time zones.
• Perform and debug LVS, DRC, PERC, ERC and other signoffs with industry tools.
• Contribute to chip-level planning including floor planning and power grid design.
• Lead layout design reviews and ensure quality, verification and schedule adherence.
• Support automation through scripting (SKILL, TCL, Python).

Skills

Analog layout

FinFET experience

IP/layout macros

Device matching

Layout verification

Tools

Cadence Virtuoso

Calibre

Pegasus

Scripting: Python

Job description

Celero Communications, Inc. in Irvine, CA is seeking a Principal High-Speed Analog Layout Design Engineer to lead the layout of complex analog/mixed-signal IP blocks integral to advanced optical communications systems.

You will mentor junior engineers, drive floor planning and power grid implementation, and coordinate with circuit designers, CAD/PDK teams, and international teams to ensure first-pass silicon success.