Senior High-Speed Analog Layout Architect

Celero Communications, Inc.; United States; Remote; USD 140,000 - 230,000; Full time

Job summary

Celero Communications, Inc. seeks a Principal High-Speed Analog Layout Engineer to lead the layout of complex analog/mixed-signal IP blocks for advanced optical communication systems.

You will mentor engineers, collaborate with circuit designers and CAD/PDK teams, and drive layout from floor planning to verification. The role requires deep device physics knowledge, a track record on FinFET nodes, and leadership in IP layout or full-chip implementations.

Qualifications

• 10+ years of hands-on analog/mixed-signal layout design in advanced CMOS/FinFET tech.
• Leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes.
• Experience with TSMC FinFET nodes (N3/N5/N7/N16).
• Deep understanding of LOD, WPE, OSE, LDE and their impact on performance.
• Layout best practices for matching, noise isolation, ESD, symmetry and minimization of parasitics.
• Floor planning, hierarchical block integration, routing strategy and power/ground design.
• Familiarity with LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules; collaboration across teams.

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through final verification.
• Collaborate with schematic designers to create layout solutions with performance and reliability in mind.
• Mentor junior layout engineers across multiple time zones, enforcing best practices.
• Perform and debug LVS, DRC, PERC, ERC and other signoff checks using industry-standard tools.
• Contribute to chip-level planning including top-level floor planning, block integration, power grid, and routing.
• Participate in layout design reviews and drive layout quality, verification completeness, and schedules.
• Support automation through scripting and tool customization (SKILL, TCL, Python).

Skills

Analog/mixed-signal layout

Leadership in IP layout

TSMC FinFET experience

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Celero Communications, Inc. seeks a Principal High-Speed Analog Layout Engineer to lead the layout of complex analog/mixed-signal IP blocks for advanced optical communication systems.

You will mentor engineers, collaborate with circuit designers and CAD/PDK teams, and drive layout from floor planning to verification. The role requires deep device physics knowledge, a track record on FinFET nodes, and leadership in IP layout or full-chip implementations.