Senior High-Speed Analog ASIC Layout Engineer

Micron Technology, Inc.; Minneapolis (MN); On-site; USD 74,000 - 127,000; Full time

Benefits offered by this job

Healthcare benefits

Paid time off

Holidays

Job summary

Micron Technology, Inc. is seeking an ASIC Analog Layout Engineer to drive high-speed analog/mixed-signal layouts for tester and controller IP. You will partner with analog designers to optimize performance, manage parasitics, and ensure manufacturability in deep sub-micron processes.

The role emphasizes LVS/DRC/ERC checks, layout automation, and AI-enabled productivity. A strong background in SerDes/PLL/DLL and high-speed circuits is required.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Experience with Cadence Virtuoso or similar tool for analog/mixed-signal layouts.
• Experience with DRC, LVS, ERC and antenna rule closure.
• Experience applying analog layout fundamentals to optimize performance/manufacturability.

Responsibilities

• Develop high-quality analog/mixed-signal layouts for high-speed ASICs.
• Collaborate with analog design engineers on feasible, manufacturable layouts.
• Perform and debug LVS/DRC/ERC and antenna checks.
• Optimize layouts for parasitics, signal integrity and ESD robustness.
• Contribute to layout methodologies and process improvements.
• Develop automation, scripting and AI-enabled layout productivity tools.
• Troubleshoot CAD/tool issues in the layout environment.
• Support layout for SerDes, PLL, DLL, TX/RX, clocking circuits and PHY blocks.

Skills

4+ years experience in analog/mixed-s

SerDes/PHY/PLL/DLL expertise

Parasitic analysis

Automation scripting

Advanced-node layout

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering

Tools

Cadence Virtuoso

Job description

Micron Technology, Inc. is seeking an ASIC Analog Layout Engineer to drive high-speed analog/mixed-signal layouts for tester and controller IP. You will partner with analog designers to optimize performance, manage parasitics, and ensure manufacturability in deep sub-micron processes.

The role emphasizes LVS/DRC/ERC checks, layout automation, and AI-enabled productivity. A strong background in SerDes/PLL/DLL and high-speed circuits is required.