Pre-Silicon Verification Architect | UVM/Formal

Intel Corporation; Folsom (CA); Hybrid; USD 164,000 - 232,000; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health, retirement, and vacation.

Job summary

Intel Corporation in California is seeking an experienced verification architect to define and implement pre-silicon verification strategies, architect testbenches, and integrate block testbenches into chip-level UVM environments.

You will develop test strategies and plans for design blocks, coordinate with analog and digital teams for post-silicon validation, and contribute to security validation to improve coverage, with a hybrid on-site/off-site work model.

Qualifications

• Bachelor's degree with 10+ years of relevant industry experience, or a Master's with 8+ years.
• Experience with IP/SoC pre-silicon validation and SystemVerilog tooling (VCS/Verdi).
• IP environment and configuration management tools.
• UVM methodology.

Responsibilities

• Define, architect, and document verification strategy for pre-silicon design.
• Architect testbenches and develop UVM or formal verification approaches.
• Integrate block testbenches in chip-level UVM environments and verify integration.
• Develop test strategy, testbench architecture, and test plans for design blocks.
• Coordinate with analog and digital teams and support post-silicon validation.
• Create random test generation plans and perform functional simulations to find gaps in design specifications.
• Conduct failure analysis, coverage analysis, and closure.

Skills

SystemVerilog

UVM

IP/SoC pre-silicon validation

Formal verification

VCS/Verdi

DDR/DFI/LPDDR protocols

Education

Bachelor's degree with 10+ years of relevant industry experience

Master's degree with 8+ years of relevant industry experience

Tools

VCS

Verdi

VSCode

GitHub Copilot

Job description

Intel Corporation in California is seeking an experienced verification architect to define and implement pre-silicon verification strategies, architect testbenches, and integrate block testbenches into chip-level UVM environments.

You will develop test strategies and plans for design blocks, coordinate with analog and digital teams for post-silicon validation, and contribute to security validation to improve coverage, with a hybrid on-site/off-site work model.