Senior Hardware Verification Engineer: IP & SOC Testbenches

Baya Systems; Austin (TX); On-site; USD 100,000 - 150,000; Full time

Job summary

A technology company in Austin, TX, is seeking a Senior Hardware Verification Engineer to contribute to the technology portfolio. The ideal candidate will have at least 8 years of experience in verification and proficiency in Verilog and SystemVerilog. Responsibilities include collaborating with design and software teams to create test plans and implement testbenches. Excellent problem-solving and communication skills are essential for this role.

Qualifications

• 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification.
• Deep experience with UVM-based testbenches.
• Knowledge of ARM AMBA protocols such as AXI, APB, and AHB.

Responsibilities

• Collaborate with design and architecture teams to create test plans for configurable IPs.
• Write UVM/SystemVerilog code to implement the test plan.
• Work with design and DV engineers to implement the test plan and debug failures.

Skills

Verilog

SystemVerilog

Python

UVM-based testbenches

Problem-solving skills

Communication skills

Education

BS/MS in Electrical Engineering, Computer Engineering or Computer Science

Tools

EDA tools for simulation and debug

Job description

A technology company in Austin, TX, is seeking a Senior Hardware Verification Engineer to contribute to the technology portfolio. The ideal candidate will have at least 8 years of experience in verification and proficiency in Verilog and SystemVerilog. Responsibilities include collaborating with design and software teams to create test plans and implement testbenches. Excellent problem-solving and communication skills are essential for this role.