Senior Hardware Engineer, ML Acceleration & SoC

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 183,000 - 248,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs (U.S.) Inc. within AWS UC is seeking a Hardware Design Engineer to define, design and validate the next generation ML chips, cards and server integration.

As a senior member of the hardware team, you will lead PCIe and Serdes topics to build customized platforms for AWS data centers in Cupertino. You will work across silicon and software stacks, applying new technologies to large-scale deployments, with high standards for performance, reliability and cost.

Qualifications

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience.
• 7+ years of digital design in communication systems experience
• 7+ years of full-custom analog or RF layout experience
• 7+ years of wireless communications systems and implementation experience
• 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience
• 7+ years of verification in communication systems experience
• 5+ years of UVM, C, System C, and scripting experience
• 3+ years of emulation experience
• Bachelor's degree in Electrical Engineering or a related field
• Knowledge of UVM and Matlab
• Knowledge of implementing chips with multiple power islands and power gating
• Knowledge of multiple access systems including OFDMA, TDMA, and CDMA
• Knowledge of end‑to‑end network system architecture from wireless physical layer to application endpoints
• Knowledge of serial protocols including SPI, I2C, I3C, and UART
• Knowledge of Python and Embedded C programming
• Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering
• Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards
• Experience leading or solely developing methodology and scripts for physical synthesis
• Experience taping out chips that have gone into high volume production
• Experience developing products for volume production
• Experience low power design techniques
• Experience delivering products to volume production
• Experience in modem L1/L2 algorithms development and architectures
• Experience in developing link and system level simulators using MATLAB, Python, or C++
• Experience in test setup automation using MATLAB, Python, or Pearl
• Experience with Agile, TDD, BDD, CI, and Git
• Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general‑purpose processors
• Experience leading technical initiatives and key deliverables
• Experience with version control systems and CI/CD pipeline implementation
• Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC

Responsibilities

• Define and validate next-gen AWS ML chips, cards and server integration.
• Lead PCIe and Serdes topics to build customized platforms for AWS datacenters.
• Collaborate across silicon and software stacks to deliver high-performance, scalable hardware solutions.
• Drive reliability, power efficiency and cost optimization for volume production.

Skills

ASIC implementation

Digital design

Analog/RF layout

Wireless systems

Post-Silicon automation

Verification

UVM

C

Python

MATLAB

Embedded C

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering (preferred)

Tools

MATLAB

C/C++

Python

SPI/I2C/I3C/UART

Verilog/VHDL

CI/CD tooling

Job description

Annapurna Labs (U.S.) Inc. within AWS UC is seeking a Hardware Design Engineer to define, design and validate the next generation ML chips, cards and server integration.

As a senior member of the hardware team, you will lead PCIe and Serdes topics to build customized platforms for AWS data centers in Cupertino. You will work across silicon and software stacks, applying new technologies to large-scale deployments, with high standards for performance, reliability and cost.