Sr. Hardware Engineer - ML Acceleration, Annapurna Labs (AWS)

Amazon; Cupertino (CA); On-site; USD 143,300 - 247,600; Full time

Job summary

Amazon’s Annapurna Labs unit seeks a Sr. Hardware Engineer to define, design, and validate next‑gen AWS ML chips, cards, and server integration for datacenter use. You will lead PCIe, SerDes, and high‑speed interfaces to deliver top performance and cost efficiency.

Responsibilities include hardware design validation, test development, and cross‑functional collaboration with software teams to implement diagnostics and validation processes.

Qualifications

• Deep knowledge of PCIe Gen4 or above, electrical and functional at chip and PCB levels.
• Deep understanding of transmission line theory and electromagnetics, for SerDes and interfaces.
• Experience working with ODMs, IP silicon vendors, and suppliers on triaging and debugging.
• Hands‑on lab equipment skills (VNA, real‑time scope, sampling scope) for validation.
• Automation scripting skills for test execution, log parsing, and data collection.
• Strong technical communication skills to interface with cross‑functional leads.

Responsibilities

• Design and validate hardware for AWS ML chips and server integration.
• Lead PCIe and SerDes design and integration efforts.
• Shape and optimize high‑speed interface design and signal integrity.
• Drive test development, automation, and data collection.
• Collaborate with software and hardware teams to define diagnostics and validation processes.

Skills

PCIe Gen4 expertise

Transmission line theory

ODM / silicon vendor coordination

Lab equipment for validation

Automation scripting for tests

Technical communication

Job description

Sr. Hardware Engineer - ML Acceleration, Annapurna Labs

As a senior member of the Machine Learning Acceleration team, you will define, design, and validate next‑generation AWS ML chips, cards, and server integration. You will lead the design and optimization of hardware for AWS datacenters, focusing on PCIe, SerDes, and high‑speed interfaces to deliver world‑class performance, quality, and cost efficiency.

Responsibilities

Design and validate hardware for AWS ML chips and server integration.

Lead PCIe and SerDes design and integration efforts.

Shape and optimize high‑speed interface design and signal integrity.

Drive test development, automation, and data collection.

Collaborate cross‑functionally with software and hardware teams to define diagnostics and validation processes.

Basic Qualifications

• Deep knowledge of PCIe Gen4 or above, both electrical and functional at the chip and PCB levels.
• Deep understanding of transmission line theory and electromagnetics, and application to SerDes, single‑ended signal, and parallel bus interfaces.
• Experience working with ODMs, IP silicon vendors, component suppliers, and internal design teams on triaging, debugging, and resolving issues.
• Hands‑on lab equipment skills (VNA, real‑time scope, sampling scope, and accessories) for electrical validation and characterization.
• Automation scripting skills for test execution, log parsing, and data collection.
• Strong technical communication skills (verbal and written) to interface with cross‑functional technical leads.

Preferred Qualifications

• Experience with server hardware designs, design validation, production tests, and signal integrity of high‑speed interfaces.
• Knowledge of the product development cycle from concept to mass production.
• Strong analytical capabilities.
• Ability to work independently and drive tasks from start to completion.
• Experience collaborating with software teams to implement diagnostics for hardware validation at component, interface, and system levels.
• Experience with server (x86 / ARM) design or architecture.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Compensation: The base pay for this position ranges from $143,300 per year in the lowest geographic market to $247,600 per year in the highest geographic market. Additional equity, sign‑on bonuses, and benefits may be provided as part of a total compensation package.