Senior ML Acceleration Hardware Engineer

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,000 - 215,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a Hardware Design Engineer to define, design and validate next-generation ML chips, cards, and server integration. You will lead PCIe and Serdes topics and contribute to scalable datacenter hardware platforms.

The role requires extensive ASIC/digital design, RF/analog experience, and wireless systems knowledge, with emphasis on verification, automation, and post-silicon readiness. Collaboration across teams is essential.

Qualifications

• 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience.
• 7+ years of digital design in communication systems experience.
• 7+ years of full-custom analog or RF layout experience.
• 7+ years of wireless communications systems and implementation experience.
• 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience.
• 7+ years of verification in communication systems experience.
• 5+ years of UVM, C, System C, and scripting experience.
• 3+ years of emulation experience.
• Knowledge of UVM and Matlab.
• Knowledge of implementing chips with multiple power islands and power gating.
• Knowledge of multiple access systems including OFDMA, TDMA, and CDMA.
• Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints.
• Knowledge of serial protocols including SPI, I2C, I3C, and UART.
• Experience with Agile, TDD, CI, and Git.
• Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors.
• Experience leading technical initiatives and key deliverables.

Responsibilities

• Contribute to the design and validation of AWS next-generation ML chips, cards and server integration.
• Lead the development and optimization of PCIe and Serdes topics for scalable datacenter deployments.
• Deliver high-quality hardware designs with attention to performance, power, and cost targets.

Skills

ASIC implementation

Digital design

Wireless communications

Verification

C / SystemC / scripting

Emulation

Python

Embedded C

MATLAB

PHY/MAC HW/SW

Education

Bachelor's degree in Electrical Engineering or related field

Tools

MATLAB

Python

C

SystemC

Job description

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a Hardware Design Engineer to define, design and validate next-generation ML chips, cards, and server integration. You will lead PCIe and Serdes topics and contribute to scalable datacenter hardware platforms.

The role requires extensive ASIC/digital design, RF/analog experience, and wireless systems knowledge, with emphasis on verification, automation, and post-silicon readiness. Collaboration across teams is essential.