ML Acceleration Engineer – Pre-Silicon HW/SW Co‑Design

Amazon; Austin (TX); Sur place; USD 157 300 - 212 800; Plein temps

Résumé du poste

Amazon's Annapurna Labs is seeking an SDE to drive pre-silicon hardware/software co-design for our machine learning acceleration chips. You will collaborate with architecture, design and emulation teams to implement new silicon functionality and write bare-metal software to verify end-to-end SoC performance.

In this role you will tackle multi-level verification, debug complex systems, and contribute to pre-silicon verification workflows, with opportunities to shape next-gen ML hardware in a

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong debugging skills.
• Experience verifying at multiple logic levels from IP blocks to SoCs to full system testing.
• Preferred: Master's degree in Electrical/Communications Engineering.
• Experience with ARM and various DSP ISAs and RF/wireless standards is a plus.

Responsabilités

• Drive pre-silicon hardware/software co-development for ML accelerator SoCs.
• Collaborate with architecture, design and emulation teams to implement silicon functionality.
• Write bare‑metal software to verify end‑to‑end SoC functionality and subsystem performance.

Connaissances

Debugging

Verification

Bare-metal development

End-to-end verification

System-level debugging

Formation

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Communications Engineering

Outils

Python

Perl

ARM ISAs

DSP ISAs

Description du poste

Amazon's Annapurna Labs is seeking an SDE to drive pre-silicon hardware/software co-design for our machine learning acceleration chips. You will collaborate with architecture, design and emulation teams to implement new silicon functionality and write bare-metal software to verify end-to-end SoC performance.

In this role you will tackle multi-level verification, debug complex systems, and contribute to pre-silicon verification workflows, with opportunities to shape next-gen ML hardware in a