Senior GPU Physical Design Engineer - PPA Innovator

Samsung Electronics America; Austin (TX); On-site; USD 180,000 - 270,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Life insurance

401(k)

Onsite lunch

Tuition assistance

Paid time off

Job summary

Samsung Electronics America is seeking a Senior Staff GPU Physical Design Engineer to lead physical implementation for high-performance GPU IP, focusing on top-level floorplanning, power-grid design, and scalable execution across advanced nodes.

You will collaborate with architecture, RTL, software, and system-level teams to deliver robust silicon, drive methodology innovations, and mentor junior engineers in a fast-paced, global environment.

Qualifications

• 10+ years with a Bachelor’s Degree in CS/Engineering (or 8+ with a Master’s, or 6+ with a Ph.D.)
• 7+ years hands-on experience with full physical design flow: synthesis, P&R, CTS, timing closure, signoff
• Strong top-level floorplanning, low-power design, physical verification, and advanced-node challenges
• Power-grid design experience with PNR tools and robustness analysis

Responsibilities

• Lead top-level floorplanning for GPU/SoC designs
• Shape power-grid implementation and optimization
• Drive STA-based convergence and timing closure
• Contribute to full-chip/large IP implementation and signoff
• Mentor junior engineers and share design methodology
• Collaborate with architecture, RTL, and external vendors

Skills

Top-level floorplanning

Power-grid design

Timing closure

Place-and-route

EDA tool fluency

Python/Tcl scripting

Cross-functional collaboration

Mentoring

Problem solving

Education

Bachelor’s degree in CS/Engineering

Master’s degree in CS/Engineering

Ph.D.

Tools

FusionCompiler

Innovus

ICC2

Fusion Compiler

PrimeTime/Tempus

StarRC

Job description

Samsung Electronics America is seeking a Senior Staff GPU Physical Design Engineer to lead physical implementation for high-performance GPU IP, focusing on top-level floorplanning, power-grid design, and scalable execution across advanced nodes.

You will collaborate with architecture, RTL, software, and system-level teams to deliver robust silicon, drive methodology innovations, and mentor junior engineers in a fast-paced, global environment.