Senior GPU Physical Design Architect

Samsung Electronics Perú; Austin (TX); On-site; USD 180,000 - 270,000; Full time

Job summary

Samsung Austin Research and Development Center (SARC) is seeking a Senior Staff GPU Physical Design Engineer to shape physical implementation for high‑performance GPU IP. You will drive synthesis through signoff, optimize power, performance and area, and lead methodology innovations while collaborating with architecture, RTL, and software teams.

You will mentor engineers, advance DTCO and node challenges, and contribute to scalable design practices in a fast‑paced, global environment.

Qualifications

• 11+ years with BS, 9+ with MS, or 7+ with PhD in relevant fields.
• 7+ years hands-on with full physical design flows: synthesis to signoff.
• Strong GPU/SoC physical design, low-power, DRC/LVS, advanced-node challenges.
• Experience with timing analysis, convergence, STA, signal integrity and reliability.
• Proficient with industry-standard EDA tools and scripting in Python/Tcl/Shell/Perl.
• Excellent collaboration and communication in a global team.

Responsibilities

• Shape full-chip and block-level implementation from synthesis through signoff.
• Improve methodologies, automation, and flow across projects.
• Collaborate with architecture, RTL, software and system teams to resolve issues.
• Mentor junior engineers and drive technical initiatives and innovation.

Skills

Physical design expertise

Synthesis

Place-and-route

CTS

Timing closure

Signoff

Low-power design

EDA tools proficiency

Python scripting

Tcl scripting

Shell scripting

Perl scripting

Collaboration and communication

Education

Bachelor’s Degree in CS/Engineering

Master’s Degree in CS/Engineering

Ph.D. in related field

Tools

ICC2/Fusion Compiler/Innovus

PrimeTime/Tempus

StarRC

Job description

Samsung Austin Research and Development Center (SARC) is seeking a Senior Staff GPU Physical Design Engineer to shape physical implementation for high‑performance GPU IP. You will drive synthesis through signoff, optimize power, performance and area, and lead methodology innovations while collaborating with architecture, RTL, and software teams.

You will mentor engineers, advance DTCO and node challenges, and contribute to scalable design practices in a fast‑paced, global environment.