Senior GPU Frontend & Implementation Engineer

Qualcomm; San Diego (CA); On-site; USD 195,000 - 293,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a Design Implementation Engineer for the Adreno GPU team in San Diego, CA.

The role focuses on front end implementation challenges and delivering state-of-the-art GPU cores while coordinating with graphics, RTL, and physical design teams to meet aggressive PPA targets. You will work hands-on with new flows and methodologies to drive power, performance, and area improvements.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field with 5+ years of direct front end implementation and physical design work experience.
• Master’s degree in Electrical/Computer Engineering or related field with 4+ years of direct front end implementation and physical design work experience.
• PhD in Electrical/Computer Engineering or related field with 5+ years of direct front end implementation and physical design work experience.
• Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools
• Hands on experience taping out designs in sub-micron technology node design
• Expect strong self-motivation and time management skills

Skills

Front end implementation

CMOS design understanding

GPU micro-architecture knowledge

Scripting (tcl, perl, python)

Strong debugging/analytical skills

Team collaboration

Education

Bachelors in Electrical/Computer Engineering or related

Masters in Electrical/Computer Engineering or related

PhD in Electrical/Computer Engineering or related

Tools

Synthesis & Place & Route tools including Signoff

Synopsys Next Generation tools

Conformal LEC

Synopsys Formality

Synopsys PrimeTime

Job description

Qualcomm Technologies, Inc. is seeking a Design Implementation Engineer for the Adreno GPU team in San Diego, CA.

The role focuses on front end implementation challenges and delivering state-of-the-art GPU cores while coordinating with graphics, RTL, and physical design teams to meet aggressive PPA targets. You will work hands-on with new flows and methodologies to drive power, performance, and area improvements.