Hardware Design Engineer - Graphics Silicon Implementation

Qualcomm; San Diego (CA); On-site; USD 161,800 - 242,600; Full time

Benefits offered by this job

Competitive annual discretionary bonus program

Opportunities for annual RSU grants

Job summary

Qualcomm in San Diego is seeking an Engineer for the Adreno GPU team, focusing on implementation and methodology of Adreno Graphics cores. The role involves RTL integration and requires a Bachelor's degree in a relevant field along with experience in Verilog and System Verilog.

The successful candidate will be responsible for various integration processes, collaborating across multiple teams to ensure design quality. Qualcomm offers a competitive salary range from $161,800 to $242,600, as well as bonuses and comprehensive benefits.

Qualifications

• 0-5 years relevant industry experience.
• Understanding of digital design and RTL development using Verilog/System Verilog.
• Basic knowledge of synthesis, static timing, timing closure, and formal verification.

Responsibilities

• Work on Qualcomm's Adreno Graphics cores in implementation and methodology.
• Collaborate with Architecture, Design, DV, SOC, DFT, and IMPL teams.
• Package, qualify, and deliver FE design collateral.

Skills

Verilog and System‑Verilog languages

RTL integration

Version control systems

UNIX, Perl, TCL or shell scripting

ECO methods for functional and timing fixes

PPA optimization techniques

Education

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field

Tools

Synopsys Design Compiler

Synopsys PrimeTime

Job description

Job Summary

Qualcomm CDMA Technologies is the world leader in wireless ICs powering the majority of 3G & 4G devices and the largest fabless semiconductor company in the world. The Graphics team is looking for an Engineer to work on Qualcomm's Adreno Graphics cores in the area of implementation and methodology. The successful candidate will work in the Adreno GPU team and will be responsible for various functions from RTL integration through to physical design.

Knowledge and Experience

• Verilog and System‑Verilog languages
• RTL integration, partitioning, transformation, and analysis
• Ensure implementation readiness with RTL lint, custom checks, unit level synthesis and clock domain crossing checks
• Package, qualify and deliver FE design collateral
• Develop innovative methods to improve front‑end design integration process
• Collaborate effectively with Architecture, Design, DV, SOC, DFT, and IMPL teams spanning multiple sites
• Version control systems
• RTL synthesis using physically aware tools
• Formal Verification using industry standard tools for RTL‑netlist and netlist‑netlist checks
• ECO methods for functional and timing fixes
• Managing design goals in power, performance and area

Minimum Skills

• 0-5 years relevant industry experience
• Digital design and RTL development understanding using Verilog and/or System Verilog
• Basic level knowledge of synthesis, static timing, timing closure, constraints and formal verification
• Exposure to Synopsys Design Compiler tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime

Preferred Skills

• Experience with UNIX, Perl, TCL or shell scripting
• Ability to analyze architectural and micro architectural details to drive design partitioning
• Knowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA
• Excellent interpersonal and analytical skills as well as ability to work independently
• Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience
• Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience
• PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience

Salary & Benefits

$161,800.00 - $242,600.00. The pay scale reflects the broad, minimum to maximum, pay scale for this job code for the specified location. In addition, Qualcomm offers a competitive annual discretionary bonus program and opportunities for annual RSU grants. A highly competitive benefits package supports success at work, at home, and at play.

EEO

Qualcomm is an equal opportunity employer. Qualcomm is committed to providing an accessible process for individuals with disabilities and will provide reasonable accommodations to support individuals with disabilities in the hiring process.